View NCV7424_7869845.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? semiconductor components industries, llc, 2013 august, 2013 ? rev. 0 1 publication order number: NCV7424/d NCV7424 four channel lin transceiver NCV7424 is a four channel physical layer device using the local interconnect network (lin) protocol. it allows interfacing of four independent lin physical buses and the lin protocol controllers. the device is compliant to lin 2.x protocol specification package and the sae j2602 standard. the NCV7424 lin device is a member of the in-vehicle networking (ivn) transceiver family. the device is a monolithic solution incorporating 4 times the ncv7321-1 transceiver. it is designed to work in a harsh automotive environment and is qualified following the ts16949 flow. features ? tssop16 package. pin-out compatible with one single lin ncv7321 transceiver (pin numbers 4 to 7, and 10 to 13) ? compliant with lin2.x, backwards compatible to version 1.3 and j2602 ? transmission rate 1 kbps to 20 kbps ? indefinite short-circuit protection on lin towards supply and ground ? bus pins protected against transients in an automotive environment ? thermal shutdown ? system esd on lin pin exceeding 10 kv, no need for external esd protections ? load dump protection (45 v) ? integrated slope control resulting into excellent eme performance also without any capacitor on lin pin ? excellent emi performance ? remote wake-up via lin bus on all four channels ? 3.3 v and 5 v compatible digital inputs ? these are pb-free devices tssop ? 16 case 948f marking diagram http://onsemi.com see detailed ordering, marking and shipping information in the package dimensions section on page 11 of this data sheet. ordering information package picture (*note: microdot may be in either location) tssop ? 16 txd4 rxd3 txd3 rxd1 en txd2 txd1 rxd2 NCV7424 1 89 16 rxd4 lin4 gnd lin3 v bb lin1 gnd lin2 1 16 nv74 24 ? 0 alyw 1 16 nv7424 ? 0 = specific device code a = assembly location l = wafer lot y = year w = work week = pb ? free package
NCV7424 http://onsemi.com 2 block diagram figure 1. block diagram lin1 NCV7424 gnd rxd1 txd1 rb20111020.1 channel2 rxd2 txd2 lin2 channel3 rxd3 txd3 lin3 channel4 rxd4 txd4 lin4 thermal shutdown undervoltage por state & wake ? up control timeouts osc vint en gnd comp slope control filter driver control vint channel1 v bb
NCV7424 http://onsemi.com 3 table 1. key technical characteristics and operating ranges symbol parameter min typ max unit v bb nominal battery operating voltage (note 1) 5 12 27 v load dump protection 45 i bb _slp supply current in sleep mode, v bb = 12 v , t j < 85 c v linx = v bb 10 30 a v lin lin bus voltage ? 45 45 v v_dig_io operating dc voltage on digital io pins (en, rxd1-4, txd1-4) 0 5.5 v t j junction thermal shutdown temperature 150 165 185 c t amb operating ambient temperature ? 40 125 c v esd electrostatic discharge voltage (all pins) human body model (note 2) conform to eia ? jesd22 ? a114 ? b ? 4 4 kv electrostatic discharge voltage (lin) system human body model (note 3) conform to eic 61000 ? 4 ? 2 ? 10 10 kv 1. below 5 v on v bb in normal mode, the bus will either stay recessive or comply with the voltage level specifications and transition time specifications as required by sae j2602. it is ensured by the battery monitoring circuit. above 27 v on v bb , lin communication is operational (lin pin toggling) but parameters cannot be guaranteed. for higher battery voltage operation above 27 v, lin pull-up resistor m ust be selected large enough to avoid clamping of lin pin by voltage drop over external pull-up resistor and lin pin min current limit ation. 2. equivalent to discharging a 100 pf capacitor through a 1.5 k resistor. 3. equivalent to discharging a 150 pf capacitor through a 330 resistor. system hbm levels are verified by an external test ? house. table 2. pin function description pin name description 1 txd4 transmit data input, low for dominant state; pull-up to internal supply guaranteed above pin input threshold 2 rxd3 receive data output; low in dominant state 3 txd3 transmit data input, low for dominant state; pull-up to internal supply guaranteed above pin input threshold 4 rxd1 receive data output; low in dominant state 5 en enable input, transceiver in normal operation mode when high, pull-down resistor to gnd 6 txd2 transmit data input, low for dominant state; pull-up to internal supply guaranteed above pin input threshold 7 txd1 transmit data input, low for dominant state; pull-up to internal supply guaranteed above pin input threshold 8 rxd2 receive data output; low in dominant state 9 lin2 lin bus output/input 10 gnd ground 11 lin1 lin bus output/input 12 v bb battery supply input 13 lin3 lin bus output/input 14 gnd ground 15 lin4 lin bus output/input 16 rxd4 receive data output; low in dominant state
NCV7424 http://onsemi.com 4 typical application figure 2. application diagram, four lin master nodes kl30 kl31 linx micro controller rxdx txdx en vbat gnd NCV7424 linx 4 4 4 4 4 vcc 2.7 v to 5 v gnd gnd 4 5.1k lin bus 1,2,3,4 gnd 1k 1nf 4 rb 20111103 v bb v bb table 3. absolute maximum ratings symbol parameter min typ max unit v bb voltage on pin v bb ? 0.3 45 v v linx linx bus voltage (lin1-4) ? 45 45 v v_dig_io dc input voltage on pins (en, rxd1-4, txd1-4) ? 0.3 6 v t j maximum junction temperature ? 40 150 c v esd hbm (all pins) (note 4) conform to eia ? jesd22 ? a114 ? b ? 4 4 kv cdm (all pins) according to esd stm 5.3.1 ? 1999 ? 750 750 v hbm (linx and v bb ) (note 4) ? 8 8 kv system hbm (linx and v bb ) (note 5) conform to eic 61000 ? 4 ? 2 ? 1 0 10 kv stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 4. equivalent to discharging a 100 pf capacitor through a 1.5 k resistor. 5. equivalent to discharging a 150 pf capacitor through a 330 resistor. system hbm levels are verified by an external test ? house.
NCV7424 http://onsemi.com 5 table 4. thermal characteristics symbol parameter conditions value unit r ja_1 thermal resistance junction ? to ? air, jesd51-3 1s0p pcb free air 128 k/w r ja_2 thermal resistance junction ? to ? air, jesd51-7 2s2p pcb free air 72 k/w functional description overall functional description lin is a serial communication protocol that efficiently supports the control of mechatronic nodes in distributed automotive applications. the domain is class-a multiplex buses with a single master node and a set of slave nodes. the NCV7424 contains four independent lin transmitters, lin receivers plus common battery monitoring, power-on-reset (por) circuits and thermal shutdown (tsd). the used lin transmitter is optimized for the maximum specified transmission speed of 20 kbps with excellent emc performance due to reduced slew rate of the lin outputs. the junction temperature is monitored via a thermal shutdown circuit that switches the lin transmitters off when temperature exceeds the tsd trigger level. the NCV7424 has four operating states (unpowered mode, standby mode, normal mode and sleep mode) that are determined by the supply voltage v bb , input signals en and activity on the lin bus. the operating states and principal transitions between them are depicted in figure 3. operating states sleep mode normal mode standby mode figure 3. state diagram lin1, 2, 3 or 4 wakeup ? lin transceivers: off ? lin term: 30 k ? rxd1, 2, 3, 4: low to indicate wake ? up on bus / floating otherwise ? lin transceivers: off ? lin term: current source ? rxd1, 2, 3, 4: floating ? lin transceivers: on ? lin term: 30 k ? rxd1, 2, 3, 4: received lin data v bb above reset level unpowered ? lin transceivers: off ? lin term: floating ? rxd1, 2, 3, 4: floating (v bb below reset level) en = high for t > t enable en = high for t > t enable en = low for t > t disable unpowered mode as long as v bb remains below its power-on-reset level, the chip is kept in a safe unpowered state. lin transmitters are inactive, linx pins are left floating. pins rxdx remain floating. the unpowered state will be entered from any other state when v bb falls below its power-on-reset level. standby mode standby mode is a low-power mode, where the lin transceivers remain inactive. a 30 k resistor in series with a reverse-protection diode is internally connected between individual lin pins and pin v bb . standby mode is entered after a wake-up event is recognized while the chip was in the sleep mode, the rxd1,2,3 or 4 pin is pulled low depending on which of the respective pins lin1,2,3 or 4 the valid lin wake-up occurred. while staying in standby mode, wake-up signaling by rxdx pins on each lin channel is fully functional. this is also in case if wake event(s) started in sleep mode but actual transition from sleep to standby was caused by preceding wake-up event on other lin channel. normal mode in normal mode, the full functionality of the lin transceivers is available. data are sent to the linx bus according to the state of txdx inputs and rxdx pins reflect the logical symbol received on the linx bus ? high-impedant for recessive and low level for dominant.
NCV7424 http://onsemi.com 6 a 30 k resistor in series with a reverse-protection diode is internally connected between lin and v bb pins. to avoid that, due to a failure of the application (e.g. software error, a short to ground, ), the lin bus is permanently driven dominant and thus blocking all subsequent communication, the signal on each txdx pin passes through an independent timer per lin channel, which releases the bus in case txdx remains low for longer than t txd_timeout . the transmission can continue once the txdx returns to high logical level. this is independent on each channel, means permanent dominant on one channel is not blocking the other channels from communication. in case the junction temperature increases above the thermal shutdown threshold, e.g. due to a short of the lin wiring to the battery and high ambient temperature, all four transmitters are disabled and lin buses are kept in recessive state independently of txdx inputs. rxdx pins are kept low during thermal shutdown. once the junction temperature decreases below the thermal shutdown release level, the transmission is enabled again. rxd pins are released from asserted thermal shutdown low level immediately when chip is below thermal shutdown threshold. as required by sae j2602, the transceiver behaves safely below its operating range ? it either continues to transmit correctly (according to its specification) or remains silent (transmits a recessive state regardless of the txdx signal). a battery monitoring circuit in NCV7424 deactivates the transmitter in normal mode if the v bb level drops below monl_vbb. transmission is enabled again when v bb reaches monh_vbb. the internal logic remains in normal mode and the reception from the lin line is still possible even if the battery monitor disables the transmission. although the specifications of the monitoring and power-on-reset levels are overlapping, it is ensured by the implementation that the monitoring level never falls below the power-on-reset level. normal mode can be entered from either standby or sleep mode when en pin is high for longer than t enable . when the transition is made from standby mode, rxdx is put high-impedant immediately after en becomes high (before the expiration of t enable filtering time). t ransmission on each linx channel is only possible for particular txdx pin starting from high to low level (if txdx pin is low when entering normal mode, transmission is not enabled). sleep mode sleep mode provides extremely low current consumption. the lin transceiver is inactive and the battery consumption is minimized. only a weak pull-up current source is internally connected between lin and v bb pins, in order to minimize current consumption even in case of lin short to gnd. sleep mode can be entered: ? after the voltage level at v bb pin rises above its power-on-reset level. rxdx pins are set high-impedant after start-up ? from normal mode by assigning a low logical level to pin en for longer than t disable . the sleep mode can be entered even if a permanent short occurs on the linx pin. if a wake-up event occurs during the transition between normal and sl eep mode (during the t disable filtering time), it will be regarded as a valid wake-up and the chip will enter standby mode with the appropriate setting of pins rxdx. lin wake ? up remote (or lin) wake-up can be recognized on all linx pins on NCV7424 when linx bus is externally driven dominant for longer than t lin_wake and a rising edge on lin occurs afterwards ? see figure 4. wake-up events can be exclusively detected in sleep mode or during the transition from normal mode to sleep mode. due to timing tolerances, valid wake-up events beginning shortly before normal-to-sleep mode transition can be also sometimes regarded as valid wake ? ups. lin recessive level linx detection of remote wake ? up sleep mode standby mode lin dominant level figure 4. lin bus wake ? up detection v bb 40% v bb 60% v bb t t lin_wake t to_stb
NCV7424 http://onsemi.com 7 electrical characteristics definitions all voltages are referenced to gnd (pins 10, 14. these pins are electrically connected inside of the package). positive currents flow into the ic. table 5. dc characteristics (v bb = 5 v to 27 v; t j = ? 40 c to +150 c; r l(lin ? vbb) = 500 , unless otherwise specified. typical values are given at v(v bb ) = 12 v and t j = 25 c, unless otherwise specified.) symbol parameter conditions min typ max unit current consumption i bb _on_rec v bb consumption normal mode; lin recessive v linx = v bb 2.3 4.7 ma i bb _on_dom v bb consumption normal mode; lin dominant txdx = low 16.5 28 ma i bb _stb v bb consumption standby mode v linx = v bb 0.22 0.45 ma i bb _slp v bb consumption sleep mode v linx = v bb 11 35 a i bb _slp_18v v bb consumption sleep mode, v bb < 18 v v linx = v bb 10 33 a i bb _slp_12v v bb consumption sleep mode, v bb = 12 v, t j < 85 c v linx = v bb 9 30 a por and v bb monitor porh_v bb power ? on reset high level on v bb v bb rising 2 3.3 4.5 v porl_v bb power ? on reset low level on v bb v bb falling 1.7 2.9 4 v monh_v bb battery monitoring high level v bb rising 4.1 4.5 v monl_v bb battery monitoring low level v bb falling 3 4 v lin transmitters vlinx_dom_losup linx dominant output voltage txdx = low; v bb = 7.3 v 1 1.2 v vlinx_dom_hisup linx dominant output voltage txdx = low; v bb = 18 v 1.4 2.0 v vlinx_rec lin recessive output voltage txdx = high; i lin = 10 a (note 6) v bb ? 1.5 v bb v ilinx_lim short circuit current limitation v linx = v bb = 18 v; txdx = low 70 140 200 ma rlinx slave internal pull ? up resistance 20 33 47 k lin receivers vlinx_bus_dom bus voltage for dominant state 0.4 v bb vlinx_bus_rec bus voltage for recessive state 0.6 v bb vlinx_rec_dom receiver threshold lin bus recessive ? dominant 0.4 0.45 0.6 v bb vlinx_rec_rec receiver threshold lin bus dominant ? recessive 0.4 0.55 0.6 v bb 6. the voltage drop in normal mode between lin and v bb pin is the sum of the diode drop and the drop at serial pull ? up resistor. the drop at the switch is negligible. see figure 1.
NCV7424 http://onsemi.com 8 table 5. dc characteristics (v bb = 5 v to 27 v; t j = ? 40 c to +150 c; r l(lin ? vbb) = 500 , unless otherwise specified. typical values are given at v(v bb ) = 12 v and t j = 25 c, unless otherwise specified.) symbol unit max typ min conditions parameter lin receivers vlinx_rec_cnt receiver centre voltage (vlinx_rec_dom + vlinx_rec_rec) / 2 0.475 0.5 0.525 v bb vlinx_rec_hys receiver hysteresis (vlinx_rec_rec ? vlinx_rec_dom) 0.05 0.1 0.175 v bb ilinx_off_dom lin output current, bus externally driven to dominant state normal mode, driver off; v bb = 12 v; txdx = high; v linx = 0 v ? 1 ? 0.37 ? 0.2 ma ilinx_off_dom_slp lin output current, bus externally driven to dominant state sleep mode, driver off; v bb = 12 v; txdx = high; v linx = 0 v ? 20 ? 8 ? 2 a ilinx_off_rec lin output current, bus in recessive state driver off; v bb < 18 v; v bb < v linx < 18 v 2 a ilinx_no_gnd communication not affected v bb = gnd = 12 v; 0 < v linx < 18 v ? 1 1 ma ilinx_no_v bb lin bus remains operational v bb = gnd = 0 v; 0 < v linx < 18 v 0 5 a c linx capacitance on linx pin not tested in production, guaranteed by design 20 30 pf pin en vil_en low level input voltage ? 0.3 0.8 v vih_en high level input voltage 2.0 5.5 v rpd_en pull ? down resistance to ground 150 350 650 k pin rxdx iol_rxdx low level output current v rxd = 0.4 v, normal mode, v linx = 0 v 1.5 4.3 ma ioh_rxdx high level output current v rxd = 5 v, normal mode, v linx = v bb ? 5 0 5 a pin txdx vil_txdx low level input voltage ? 0.3 0.8 v vih_txdx high level input voltage 2.0 5.5 v rpd_txdx pull ? up on txdx pins 60 100 150 k thermal shutdown t jsd thermal shutdown junction temperature temperature rising 150 165 185 c t jsd_hyst thermal shutdown hysteresis 5 c 6. the voltage drop in normal mode between lin and v bb pin is the sum of the diode drop and the drop at serial pull ? up resistor. the drop at the switch is negligible. see figure 1.
NCV7424 http://onsemi.com 9 table 6. ac characteristics (v bb = 5 v to 27 v; t j = ? 40 c to +150 c; r l(lin ? vbb) = 500 , unless otherwise specified. for the transmitter parameters, the following bus loads are considered: l1 = 1 k / 1 nf; l2 = 660 / 6.8 nf; l3 = 500 / 10 nf symbol parameter conditions min typ max unit lin transmitter d1 duty cycle 1 = t bus_rec(min) / (2 x t bit ) th rec(max) = 0.744 x v bb th dom(max) = 0.581 x v bb t bit = 50 s v(v bb ) = 7 v to 18 v 0.396 0.5 d2 duty cycle 2 = t bus_rec(max) / (2 x t bit ) th rec(min) = 0.422 x v bb th dom(min) = 0.284 x v bb t bit = 50 s v(v bb ) = 7.6 v to 18 v 0.5 0.581 d3 duty cycle 3 = t bus_rec(min) / (2 x t bit ) th rec(max) = 0.778 x v bb th dom(max) = 0.616 x v bb t bit = 96 s v(v bb ) = 7 v to 18 v 0.417 0.5 d4 duty cycle 4 = t bus_rec(max) / (2 x t bit ) th rec(min) = 0.389 x v bb th dom(min) = 0.251 x v bb t bit = 96 s v(v bb ) = 7.6 v to 18 v 0.5 0.590 d1e duty cycle 1 = t bus_rec(min) / (2 x t bit ) th rec(max) = 0.744 x v bb th dom(max) = 0.581 x v bb t bit = 50 s v(v bb ) = 5 v to 40 v, (notes 7 and 8) 0.39 0.5 d2e duty cycle 2 = t bus_rec(max) / (2 x t bit ) th rec(min) = 0.422 x v bb th dom(min) = 0.284 x v bb t bit = 50 s v(v bb ) = 5 v to 40 v, (notes 7 and 8) 0.5 0.59 d3e duty cycle 3 = t bus_rec(min) / (2 x t bit ) th rec(max) = 0.778 x v bb th dom(max) = 0.616 x v bb t bit = 96 s v(v bb ) = 5 v to 40 v, (notes 7 and 8) 0.41 0.5 d4e duty cycle 4 = t bus_rec(max) / (2 x t bit ) th rec(min) = 0.389 x v bb th dom(min) = 0.251 x v bb t bit = 96 s v(v bb ) = 5 v to 40 v, (notes 7 and 8) 0.5 0.6 t tx_prop_down_x propagation delay of txdx to linx. txd high to low 1.3 4.2 10 s t tx_prop_up_x propagation delay of txdx to linx. txd low to high 1.3 4.6 10 s t tx_sym_x propagation delay symmetry t trx_prop_down_x ? t trx_prop_up_x ? 2.5 ? 0.4 2.5 s t fall linx falling edge normal mode; v bb = 12 v 9 22.5 s t rise linx rising edge normal mode; v bb = 12 v 10 22.5 s t sym linx slope symmetry normal mode; v bb = 12 v ? 4 0 4 s lin receivers t rec_prop_down_x propagation delay of linx to rxdx receiver falling edge 0.1 1.6 6 s t rec_prop_up_x propagation delay of linx to rxdx receiver rising edge 0.1 1.35 6 s t rec_sym_x propagation delay symmetry t rec_prop_down_x ? t rec_prop_up_x ? 2 0.25 2 s 7. the external pull-up resistor for duty cycles on v(v bb ) = 40 v is 1 k 8. not tested in production extended battery range (5 v; 40 v) is tested on limited sample base only
NCV7424 http://onsemi.com 10 table 6. ac characteristics (v bb = 5 v to 27 v; t j = ? 40 c to +150 c; r l(lin ? vbb) = 500 , unless otherwise specified. for the transmitter parameters, the following bus loads are considered: l1 = 1 k / 1 nf; l2 = 660 / 6.8 nf; l3 = 500 / 10 nf symbol unit max typ min conditions parameter mode transitions and timeouts t linx_wake duration of linx dominant for detection of wake ? up via linx bus sleep mode 30 90 150 s t to_stb delay from lin bus dominant to recessive edge to entering of standby mode after valid lin wake ? up see figure 4 2 2.8 18.5 s t enable duration of high level on en pin for tran ? sition to normal mode 2 18 47 s t disable duration of low level on en pin for tran ? sition to sleep mode 2 7.5 18.5 s t txd_timeout txd dominant timeout normal mode, txd = low, guaran ? tees baudrate as low as 1 kbps 15 28 50 ms 7. the external pull-up resistor for duty cycles on v(v bb ) = 40 v is 1 k 8. not tested in production extended battery range (5 v; 40 v) is tested on limited sample base only t bus_dom(min) linx t th rec(max) th rec(min) th dom(max) th dom(min) t bus_dom(max) t bus_rec(max) t bus_rec(min) t bit t bit 50% thresholds of receiving node 1 thresholds of receiving node 2 txdx t figure 5. linx bus transmitter duty cycle
NCV7424 http://onsemi.com 11 linx t 60% 40% 60% 40% 100% 0% figure 6. linx bus transmitter rising and falling times t fall t rise 50% t rec_prop_up rxdx t linx t t rec_prop_down figure 7. linx bus receiver timing 60% v bb 40% v bb v bb figure 8. linx transmitter timing 50% t bit txdx linx t t tx_prop_down t t bit t tx_prop_up v bb 60% v bb 40% v bb ordering information part number description temperature range package shipping ? NCV7424db0r2g quad lin transceiver ? 40 c to +125 c tssop16 green (pb ? free) 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
NCV7424 http://onsemi.com 12 package dimensions tssop ? 16 case 948f issue b ??? ??? ??? dim min max min max inches millimeters a 4.90 5.10 0.193 0.200 b 4.30 4.50 0.169 0.177 c ??? 1.20 ??? 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.18 0.28 0.007 0.011 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash. protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane ? w ? . section n ? n seating plane ident. pin 1 1 8 16 9 detail e j j1 b c d a k k1 h g ? u ? s u 0.15 (0.006) t s u 0.15 (0.006) t s u m 0.10 (0.004) v s t 0.10 (0.004) ? t ? ? v ? ? w ? 0.25 (0.010) 16x ref k n n 7.06 16x 0.36 16x 1.26 0.65 dimensions: millimeters 1 pitch soldering footprint on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 NCV7424/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

▲Up To Search▲

Price & Availability of NCV7424

	To Download NCV7424 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .